Digital Design Group
Intended learning outcomes
Demonstrate, through practice, the use of VHDL as a modelling language to describe digital logic, including use of common templates to describe combinational and sequential logic blocks; Explain the hardware implications of a given piece of VHDL code and the limitations imposed in coding for synthesis; Design combinational and sequential logic blocks and finite-state machines in VHDL based on a given set of functional specifications; Interpret a specification for a digital system; Propose modular structural divisions for a complex digital system, and define interfaces for the constituent modules; Set-up and run simulations and debug VHDL code for correct functionality in the ModelSim simulator, and approach the testing and simulation of a design in a systematic manner; Use Xilinx to prototype designs in FPGAs; Familiarity with good practice in design management and effective collaboration in a shared group project. Teaching details Teaching will be delivered through a combination of synchronous and asynchronous sessions, including lectures, practical activities supported by drop-in sessions, problem sheets and self-directed exercises.
Assignment 1 : An individual take-home exercise that is assessed based on functionality and quality of VHDL code, and analytical and descriptive answers, all related to design of digital circuits and systems. (ILOs 1-6) Marked on a Pass/Fail basis
Assignment 2 : A group exercise that is assessed based on the functionality and quality of submitted code to meet specifications (ILOs 1-8). Marked on a Pass/Fail basis
Reading and References
Douglas L Perry, VHDL : Programming by Example, 4th Edition, McGraw-Hill 2002.
Volnei Pedroni Circuit Design with VHDL, MIT Press, 2004
J. Bhasker, A VHDL Synthesis Primer, 2nd ed, Star Galaxy Pub., 1998.